1. Field of the Invention
The present invention relates to a static semiconductor memory device and a method of testing the same and in particular to a static semiconductor memory device capable of creating a condition comparable to the low temperature test environment at the normal temperature or at high temperature and a method of testing the same.
2. Description of the Background Art
FIG. 31 is a circuit diagram showing the detail of a memory cell of a static random access memory (referred to as an SRAM hereinafter) as a conventional static semiconductor memory device.
Referring to FIG. 31, the conventional SRAM memory cell includes driver transistors 57 and 59, access transistors 53 and 55, and high resistance elements 61 and 63. A bit line BL is connected to an NMOS transistor 43 as a bit line load, and a bit line/BL is connected to an NMOS transistor 45 as a bit line load.
A read operation thereof will now be described. When it is assumed that a storage node SN1 is at a high level and the potential of a storage node SN2 is at a low level, and driver transistor 57 is turned off and drive transistor 59 is turned on. Assuming that the potential of a word line WL is at low level and is not in a selected state, access transistors 53 and 55 are both turned off. When the potential of word line WL attains high level and its state is changed to a selected state, access transistors 53 and 55 are both turned on.
Then, a direct current, that is, a column current flows through a route of a power supply 41.fwdarw.NMOS transistor 45.fwdarw.bit line/BL.fwdarw.access transistor 55.fwdarw.driver transistor 59.fwdarw.a ground 65. The instantly flowing column current increases the potential level of ground 65 serving as the source of driver transistor 59, and as a result, the potential of storage node SN2 at the low level is slightly increased. The potential of storage node SN2 exactly at the instant when word line WL rises is represented by v0+v1, wherein v1 represents the increased potential and v0 represents the drain potential of driver transistor 59 by on-resistance of driver transistor 59. The potential settles down at v0 when a certain time period elapses.
Furthermore, since the potential of storage node SN2, serving as the gate potential of driver transistor 57, is slightly increased, the state of driver transistor 57 is changed from the non-conductive state to a slightly conductive state. This causes the potential of storage node SN1 to drop from the high level. The potential of storage node SN1 exactly at the instant when word line WL rises is represented by a power supply voltage Vcc-v2, wherein v2 represents the amount of the potential drop.
Data-hold characteristics are determined by the relation in magnitude between the potential of storage node SN1 exactly at the instant when word line WL rises, i.e., Vhold-v2, and the potential of storage node SN2, i.e., v0+v1, wherein Vhold represents a power supply voltage in data-hold. More specifically, when the potential of storage node SN1 represented by Vhold-v2 is larger than that of storage node SN2 represented by v0+v1, data is normally held. When the potential of storage node SN1 represented by Vhold-v2 is smaller than that of storage node SN2 represented by v0+v1, held data is inverted.
Thus, one of the severest conditions for data-hold of memory cells is the moment at which the difference between the potential of storage node SN1 and the potential of storage node SN2 is decreased, that is, the moment at which word line WL rises (which is a first factor causing a memory cell to be unstable). Furthermore, in order to reduce current consumption for data-hold, power supply voltage Vhold in data-hold may be reduced. This further decreases the difference between the potential of storage node SN1 and the potential of storage node SN2 and thus data inversion can be readily caused (which is a second factor causing a memory cell to be unstable). Furthermore, data inversion can be more readily caused if slight leakage current due to a slight defect or the like is caused at storage node SN1 the potential of which is held at high level (which is a third factor causing a memory cell to be unstable). Furthermore, a memory cell is rendered further unstable at low temperature (which is a fourth factor causing a memory cell to be unstable).
A cause of unstabilization of a memory cell at low temperature will now be described in detail. Change in a power supply voltage supplied from power supply 41 does not match with change in the potential of storage node SN1 supplied with the power supply voltage from power supply 41 via high resistance element 61 (i.e., the storage node which is set at a high level potential). More specifically, the potential of storage node SN1 transits with a time constant RC represented by a product of a resistance value R of high resistance element 61 and a capacitance value C of storage node SN1.
FIG. 32 illustrates a change in the potential of storage node SN1 set at high level at the normal temperature. Referring to FIG. 32, when power supply voltage Vcc is changed from a VccH level to a VccL level, the potential of storage node SN1 is also changed following the change of the power supply voltage. This also applies when the power supply voltage is changed from the VccL level to the VccH level. That is, at the normal temperature, changes in the power supply voltage supplied from power supply 41 almost matches with changes in the potential of storage node SN1 set at high level. It should be noted that high resistance elements 61 and 63 are generally formed of polysilicon. Polysilicon has temperature characteristics in conductivity and the resistance value is increased at lower temperature. Thus, the lower temperature is, the longer time (RC) a transition of the potential of storage node SN1 set at high level takes than a change of the power supply voltage supplied from power supply 41 does.
FIG. 33 illustrates change of the potential of storage node SN1 set at high level at low temperature. Referring to FIG. 33, when the power supply voltage supplied from power supply 41 is changed from the VccH level to the VccL level, the potential of storage node SN1 changes more slowly than the change of power supply voltage Vcc. This also applies when power supply voltage Vcc is changed from the VccL level to the VccH level. That is, at low temperature, a transition of the potential of storage node SN1 set at high level takes a longer time (RC) than a change of power supply voltage Vcc. Thus, if word line WL attains a high level and a memory cell is selected during a transition of the potential of storage node SN1 from the VccL level to VccH level, that is, before the potential of storage node SN1 reaches the VccL level, column current flows into the memory cell and the memory cell falls into the most unstable condition.
Memory cells are typically designed with sufficient margin so that they satisfactorily hold data even in such an unstable condition. In fact, however, unsatisfactory data hold is caused by the factors described above and thus it is required to remove an SRAM having such a defective memory cell. The unsatisfactory data hold caused by the four factors described above is herein referred to as "low temperature hold defect". In order to remove an SRAM including a memory cell having the low temperature hold defect, a test environment at low temperature is created to carry out testing in the environment.
Referring to FIG. 33, a test carried out in such a lower temperature environment will now be described. At low temperature, power supply voltage Vcc is changed from the VccL level to the VccH level at time point T0. Then a memory cell is selected and column current flows into it. Furthermore, after the potential of the storage node reaches a readable level, data is read from the memory cell. The read data is compared with written data at the normal temperature prior to placing the SRAM in the low temperature environment to determine whether a low temperature hold defect has been caused.
Thus, for conventional SRAMs, it is necessary to create a low temperature test environment for testing for low temperature hold defect and to carry out the testing in that environment. This requires enormous cost for creating the low temperature test environment.